To provide electrical conductivity between layers in a semiconductor device, a via or interconnect may be formed through an interlayer dielectric (ILD). The via is then lined with a barrier and filled with an electrically conductive material such as copper (Cu) to provide electrical conductivity between two or more metal layers, e.g., Mx and Mx+1.
A known approach for forming two-dimensional (2D) self-aligned vias (2DSAV) involves forming dummy Mx lines, e.g., formed of amorphous silicon (a-Si) and a silicon nitride (SiN) cap; patterning cuts or vias in the dummy Mx lines; forming a layer of silicon oxycarbide (SiOC) layer over the SiN cap and in the cuts; polishing back the SiOC fill to uncover the top of the dummy Mx lines; removing the Mx dummy lines, and Mx metallization. However, the polishing back of the SiOC layer increases overall production costs and time.
A need therefore exists for methodology enabling a less expensive 2DSAV formation process, and the resulting device.